Digital Voice Systems AMBE-3000 Especificações Página 33

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AMBE-3000F™ Vocoder Chip Users Manual
Version 3.4, April, 2014
Electrical Characteristics and
Requirements
1.8 V
supply voltage should not reach 0.3 V until 3v3 has reached 2.5 V. This ensures the reset signal from the I/O pin has
propagated through the I/O buffer to provide power-on reset to all the modules inside the device.
In other words, 3.3-V and 1.8-V can ramp together.
3.6 Reset Behavior
To avoid startup latency problems the system should be designed to supply a cascading reset. This means that once the system
host processor is fully functional it should bring the AMBE-3000™ Vocoder Chip out of reset using RESETn signal. The
AMBE-3000™ Vocoder Chip should then supply the CODEC_RESETn signal to bring the codec out of reset. Employing
reset in this cascading fashion will allow each device to be up and running in proper sequence so that no data is lost.
RESETn
AMBE-3000
AMBE-3000
Pin
60 (P10)
RESET*
CODEC_RESETn
Host
Processor
Host
Processor
Codec
Codec
Pin
113 (D6)
RESET*
Figure 10 Cascading Resets
Care should be taken with the AMBE-3000™ Vocoder Chip RESET pin (LQFP pin 113, BGA pin D6). The RESET pin is
considered an I/O port and will function as such when a SOFT RESET packet (PKT_RESET or PKT_RESETSOFTCFG) is
sent to the device. This means that when a SOFT RESET packet is issued, the AMBE-3000™ Vocoder Chip will pull the
RESET pin low for a short period of time (approximately 20 µsec). The designer should avoid having the AMBE-3000™
Vocoder Chip’s RESET pin be shared on the system reset line or a reset with other components on the board if there is a
chance that a SOFT RESET may be called for in the design.
3.6.1 Reset to Ready Packet Timing
RESET release to PKT_ READY is 20 msec MAX, 17 msec TYPICAL.
SOFT reset to PKT_READY = ~ 7 msec
3.6.2 Behavior of RTSn and TX_RDY following a RESET
Following a RESET, there is a short period where the TX_RDY signal is set high by the AMBE-3000. During this short period
reading of the TX_RDY should be avoided. The TX_RDY hold off period is approximately 1 msec following a reset.
(Subject to Change) Page 23
DVSI CONFIDENTIAL PROPRIETARY
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